Semiconductor Engineering

Cutting Clock Costs On The Bleeding Edge Of Process Nodes

In a recent study done by McKinsey and IDC, we see that physical design and verification costs are increasing exponentially with shrinking transistor sizes. As figure 1 shows, physical design (PD) and ...
Nature

GPS timekeeping is increasingly vulnerable: here’s how to deliver future-proofed time

Leon Lobo is the head of the National Timing Centre research and development programme at the National Physical Laboratory, Teddington, UK. Chander Velu is professor of innovation and economics at the ...