腾讯网

谈谈Verilog和SystemVerilog简史，FPGA设计是否需要学习SystemVerilog

SystemVerilog标准（SV-2009）发布距今已近十余年，在验证领域已经大放异彩，但是在设计领域（尤其FPGA领域）使用的还是比较少，虽然市场上已经发布了几本相关书籍，但是在使用上或者学习上还是有点缺陷的，这篇文章是SystemVerilog建模及仿真系列教程的第一篇 ...
电子工程专辑

[干货]用ModelSim搭建可看代码覆盖率的千兆以太网控制器的仿真环境！

对于非微电子专业做FPGA的同学们来讲，常常把仿真验证环境的搭建给忽略了，为了追求所谓的“高效”，自己写的代码根本就没怎么仿真验证过，就急急忙忙的上板调试。有的同学说也做过仿真啊，后来一看发现竟然是用Vivado等FPGA综合工具自带的仿真器来简单 ...
EDN

System Verilog for the masses

Aiming to bring advanced verification languages like SystemVerilog and advanced methods like assertion-based verification to mainstream IC designers, Mentor Graphics this week is introducing its new ...
电子工程专辑

【文档必备】Verilog、SystemVerilogIEEE标准规范

作为逻辑工程师，在FPGA和数字IC开发和设计中，一般采用verilog，VHDL或SystemVerilog等作为硬件描述语言进行工程设计，将一张白板描绘出万里江山图景。 工程师在利用硬件描述语言进行数字电路设计时，需要遵守编译器支持的Verilog,VHDL或systemverilog标准规范，并 ...
EDN

New simulation capabilities advance SystemVerilog

Santa Cruz, Calif. — Two verification providers — Mentor Graphics Corp. and Axiom Design Automation — are claiming new simulation technology this week that offers broad support for the emerging ...
Nasdaq

Lattice Diamond Software Tool Delivers New Enhancements for FPGA Design, Simulation, and ...

HILLSBORO, Ore.--(BUSINESS WIRE)-- Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced availability of the latest version of its popular FPGA design ...
Electronic Design

Assertions Lead The Way In Simulator Upgrade

One of the better bets for enhanced verification productivity these days is adoption of an assertion-based methodology. Version 6.0 of Mentor's ModelSim fully supports a standards-based approach to ...
Design-Reuse

TransEDA Again Accelerates System-On-Chip Verification with New Version of its Verification ...

Los Gatos, Calif. - January 21, 2002 - TransEDA® PLC, the leader in ready-to-use verification solutions, announced a new version of its Verification Navigator® Integrated Design Verification ...